The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2006
Filed:
Dec. 23, 2003
Boris Ratchev, Sunnyvale, CA (US);
Yean-yow Hwang, Palo Alto, CA (US);
Bruce Pedersen, San Jose, CA (US);
Boris Ratchev, Sunnyvale, CA (US);
Yean-Yow Hwang, Palo Alto, CA (US);
Bruce Pedersen, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A technique of minimizes circuit area on programmable logic with fracturable logic elements by using 'balancing' in the technology mapping stage of the programmable logic computer-aided-design flow. A fracturable LE can be used for logic implementation in many ways, such as being used as one maximum-sized look-up table (LUT) or multiple smaller LUTs. One of more inputs of the multiple smaller LUTs may be shared. By balancing, this means mean that the technology mapping algorithm is tuned to use more small LUTs and fewer maximum-sized LUTs to implement the circuit. Although this is counterintuitive since the larger LUTs are more effective at absorbing gates, the technique achieves a smaller final circuit area by packing small LUTs into fracturable LEs.