The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2006
Filed:
Jun. 09, 2004
Neal Fitzhenry, Bristol, GB;
Peter William Hughes, Bristol, GB;
Simon Christopher Dequin Clemow, Bristol, GB;
Paul Andrew Freeman, Gloucestershire, GB;
Neal Fitzhenry, Bristol, GB;
Peter William Hughes, Bristol, GB;
Simon Christopher Dequin Clemow, Bristol, GB;
Paul Andrew Freeman, Gloucestershire, GB;
Broadcom Corporation, Irvine, CA (US);
Abstract
A method for designing multi-layer electronic circuits includes defining a plurality of circuit blocks in terms of physical boundaries, the plurality of circuit blocks including a first circuit block with at least one port for connecting to a portion of inter-block routing having conducting material external to the first circuit block. The method further provides protective routing for the at least one port of the first circuit block in a region between the block and the inter-block routing, wherein circuitry within the first circuit connected to the at least one port is not in-circuit with the conducting material of the inter-block routing during processing steps involving the conducting material. The protective routing is a conducting layer which is higher in the multi-layer structure than the highest conducting layer used for routing the net containing the at least one port for inter-block routing. The protective routing also bridges the at least one port to inter-block routing connected to the net in a halo region. Software and/or a computer program product that can be used for multi-layer circuit design is also described.