The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7100136 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 29, 2006

Filed:

Jun. 28, 2002
Applicants:

Miwaka Takahashi, Kyoto, JP;

Masahiko Toyonaga, Hyogo, JP;

Inventors:

Miwaka Takahashi, Kyoto, JP;

Masahiko Toyonaga, Hyogo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Based on a relative comparison of respective consumed powers of cells which are subjected to a layout, separation information on cells to be separated which are to be arranged in a spaced-apart manner from each other is generated by separation information generating means, and a layout is generated by layout generating means based on this separation information. Accordingly, it is no more necessary to rearrange cells or to form a layout of the entire circuit again after generating an initial layout. Furthermore, it is no more necessary to set wide spacing between wirings. Still furthermore, the occurrence of noise is prevented.


Find Patent Forward Citations

Takahashi, Miwaka. (2006). Lsi design system (U.S. Patent No. 7100136). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7100136

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