The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2006
Filed:
Feb. 28, 2002
Moataz Mohamed, Irvine, CA (US);
John Spence, Villa Park, CA (US);
Kevin R. Bowles, Mission Viejo, CA (US);
Chien-wei LI, Urbana, IL (US);
Moataz Mohamed, Irvine, CA (US);
John Spence, Villa Park, CA (US);
Kevin R. Bowles, Mission Viejo, CA (US);
Chien-Wei Li, Urbana, IL (US);
Mindspeed Technologies, Inc., Newport Beach, CA (US);
Abstract
In one embodiment, move buses utilized in presently known VLIW processors are eliminated and replaced with a busing scheme which results in transfer of operands from each register file bank to any data path block while also reducing the total bus width and total power consumption associated with transport of operands from register file banks to data path blocks. According to this busing scheme, the speed of VLIW processor is also improved since the need for one clock cycle to move operands from one register file bank to another is overcome. In another embodiment, a scheduling restriction is used to eliminate the need for the presently required write back buses used by various data path blocks. In yet another embodiment, a scheduling restriction is imposed which results in a reduction of the number of ports, a reduction in the width of buses, and a reduction of power consumption.