Semiconductor integrated circuit, design support apparatus, and test method

Abstract

A semiconductor integrated circuit includes a self-testing circuit having a test circuit which is incorporated in a logic circuit to test the logic circuit. The test circuit has a test pattern generator to generate a test pattern and a compressor to compress a test result output. The logic circuit includes a plurality of scan chains including a plurality of serial connected registers and the compressor includes a through output portion. The semiconductor integrated circuit also includes a pattern counter which counts the test pattern at a test time of the logic circuit, a shift counter which counts the number of shifts in the scan chain in the logic circuit at the test time, and a failure information output circuit which is connected to the test circuit and which outputs step information of the test pattern corresponding to a failure to an integrated circuit external terminal when the failure is detected at the test time.