The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2006
Filed:
Aug. 11, 2004
Tawen Mei, Mountain View, CA (US);
Chunping Song, Santa Clara, CA (US);
Tawen Mei, Mountain View, CA (US);
Chunping Song, Santa Clara, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A method and circuit for compensating offset error caused by multiplexing in hysteretic control loops. An offset voltage, caused by one phase descending without being hysteretically controlled while another phase is being controlled, is determined by a sample-and-hold circuit that is arranged to track a low limit voltage Vand a lowest voltage V. The offset voltage is one half of a difference between Vand V. A timing and control circuit provides timing control voltages to the sample-and-hold circuit based on input signals associated with phaseand phase. The sample-and-hold circuit provides Vand Vto a differential amplifier that is arranged to provide the offset voltage to a hysteretic controller circuit. In one embodiment, the offset voltage is added to a reference voltage for corrected output voltage. In another embodiment, the offset voltage is added to the output voltage.