The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2006
Filed:
Dec. 04, 2003
Jitendra Mohan, Santa Clara, CA (US);
Luu Nguyen, San Jose, CA (US);
Alan Segervall, Half Moon Bay, CA (US);
Stephen Gee, Danville, CA (US);
Jitendra Mohan, Santa Clara, CA (US);
Luu Nguyen, San Jose, CA (US);
Alan Segervall, Half Moon Bay, CA (US);
Stephen Gee, Danville, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
The invention discloses an electrical interconnect with minimal parasitic capacitance. In one embodiment, an apparatus comprises a semiconductor substrate, and first and second support structures formed on the substrate, where the second support structure at least partially surrounds the first support structure on the substrate. The first and second support structures are each configured to support an electrical connector to be formed over the first and second support structures on the substrate.