The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2006
Filed:
Sep. 28, 2004
Yeong-gyu Lee, Kyunggi-do, KR;
Seung-do an, Kyunggi-do, KR;
Yeong-Gyu Lee, Kyunggi-do, KR;
Seung-Do An, Kyunggi-do, KR;
Samsung Electro-Mechanics Co., Ltd., Suwon-si, unknown;
Abstract
A semiconductor package and packaging method using a flip-chip bonding technology is disclosed. In the semiconductor package and packaging method, the microelement array of a micro-device, for example, the micromirror array of a light modulator having micromirrors that are hyperfine elements, is sealed from the outside using flip-chip bonding technology. Thus, the microelement array is protected from the outside. The packaging method executes the packaging process using only the flip-chip bonding technology, without a wire-bonding technology, at a wafer level instead of a conventional individual semiconductor device level, thus increasing the bonding process efficiency. Furthermore, the electrode array pattern for supplying both electricity and control signals to the microelement array does not pass through a hermetic sealing layer, thus ensuring a well-sealed semiconductor package. The electrode array pattern is also finely formed to correspond to the microelement array which is extremely finely formed.