The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2006

Filed:

Oct. 07, 2003
Applicants:

William L. Ditto, Gainesville, FL (US);

Krishnamurthy Murali, Chennai, IN;

Sudeshna Sinha, Chennai, IN;

Inventors:

William L. Ditto, Gainesville, FL (US);

Krishnamurthy Murali, Chennai, IN;

Sudeshna Sinha, Chennai, IN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A dynamically configurable logic gate can include a controller configured to provide a first threshold reference signal; an adder configured to sum the first threshold reference signal and at least one input signal to generate a summed signal; a chaotic updater configured to apply a nonlinear function to the summed signal; and a subtractor configured to determine an output signal by taking a difference between a second threshold reference signal and the processed summed signal from the chaotic updater. The logic gate can operate as one of a plurality of different logic gates responsive to adjusting at least one of the threshold reference signals.


Find Patent Forward Citations

Ditto, William. (2006). Method and apparatus for a chaotic computing module using threshold reference signal implementation (U.S. Patent No. 7096437). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7096437

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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