The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7096347 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 22, 2006

Filed:

Oct. 25, 2001
Applicant:

Charles R. Moore, Austin, TX (US);

Inventor:

Charles R. Moore, Austin, TX (US);

Assignee:

Other;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The instruction pipeline of a processor, which includes execution circuitry and instruction sequencing logic, receives a stream of instructions including a pipeline interlocking test instruction. The processor includes pipeline control logic that, responsive to receipt of the test instruction, interlocks the instruction pipeline as specified in the test instruction to prevent advancement of at least one first instruction in the instruction pipeline while permitting advancement of at least one second instruction in the instruction pipeline until occurrence of a release condition also specified by the test instruction. In response to the release condition, the pipeline control logic releases the interlock to enable advancement of said at least one instruction in the instruction pipeline. In this manner, selected instruction pipeline conditions, such a full queue or synchronization of instructions at certain pipeline stages, which are difficult to induce in a test environment through the execution of conventional instruction sets, can be tested.


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