The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2006

Filed:

May. 03, 2005
Applicants:

Manjeri Krishnan, Richardson, TX (US);

Bryan Sheffield, Rowlett, TX (US);

Joel J. Graber, Richardson, TX (US);

Duy-loan Le, Missouri City, TX (US);

Sanjive Agarwala, Richardson, TX (US);

Inventors:

Manjeri Krishnan, Richardson, TX (US);

Bryan Sheffield, Rowlett, TX (US);

Joel J. Graber, Richardson, TX (US);

Duy-Loan Le, Missouri City, TX (US);

Sanjive Agarwala, Richardson, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.


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