The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 22, 2006
Filed:
Mar. 12, 2004
Method and circuit for reducing defect current from array element failures in random access memories
Richard Parent, Shelburne, VT (US);
David Chapman, Shelburne, VT (US);
Richard Parent, Shelburne, VT (US);
David Chapman, Shelburne, VT (US);
Cypress Semiconductor Corporation, San Jose, CA (US);
Abstract
A defect current contribution elimination technique may be suitable for dynamic random access memories (DRAMs) and other memory devices. A defect current can be eliminated by using an isolation circuit () between bitlines (-and-) and an associated sense amplifier circuit (). Isolation circuit () can be controlled by programmable elements, such as fusible links, which are blown at wafer test to isolate the defective bitlines from the sense amplifier circuit. Isolated, defective bitlines may initially float, but based upon the type of defect, such bitlines can be resistively tied to another element, and as a result no DC current will flow. According to another implementation, controllable devices are placed between wordlines () and the wordline driver circuits (-). A current path through a defective wordline can be similarly cut-off.