The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 22, 2006
Filed:
Jul. 22, 2004
Charge sharing reduction by applying intrinsic parallelism in complex dynamic domino type cmos gates
Michael Haase, Duesseldorf, DE;
Wilhelm Haller, Remshalden, DE;
Rolf Sautter, Bondorf, DE;
Christoph Wandel, Weil im Schoenbuch, DE;
Michael Haase, Duesseldorf, DE;
Wilhelm Haller, Remshalden, DE;
Rolf Sautter, Bondorf, DE;
Christoph Wandel, Weil im Schoenbuch, DE;
International Business Machines Corporation, Armonk, NY (US);
Abstract
The present invention relates to dynamic hardware logic of computer processors. In particular, it relates to a method and respective system for operating a dynamic logic circuit implementing some predetermined logic function with reduced charge sharing. In order to further reduce charge sharing it is proposed to provide a predetermined number of pre-engineered switching arrangements () implementing the same logic function with a different combinatorial distribution of input variables (A, B, C), wherein each arrangement is connected between said precharged node of higher potential and a lower potential.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile