The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 22, 2006

Filed:

Apr. 15, 2004
Applicants:

Kotaro Kataoka, Tenri, JP;

Hiroshi Iwata, Nara, JP;

Akihide Shibata, Nara, JP;

Inventors:

Kotaro Kataoka, Tenri, JP;

Hiroshi Iwata, Nara, JP;

Akihide Shibata, Nara, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor memory includes: a p-type semiconductor (p-type semiconductor film on a substrate, a p-type well region in a semiconductor substrate, or an insulator); a gate insulating film formed on the p-type semiconductor; a gate electrode formed on the gate insulating film; two charge storage sections formed on side walls of the gate electrode; a channel region provided below the gate electrode; and a first n-type diffusion layer region and a second n-type diffusion layer region provided to sides of the channel region, wherein: the charge storage sections are arranged to change an electric current flow between the first n-type diffusion layer region and the second n-type diffusion layer region under application of a voltage to the gate electrode according to the quantity of electric charges stored in the charge storage sections; and the first n-type diffusion layer region is set to a reference voltage, the other n-type diffusion layer region is set to a voltage greater than the reference voltage, and the gate electrode is set to a voltage greater than the reference voltage. Thus, the semiconductor memory obtained is capable of 2 bit operation and easy to miniaturize.


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