The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2006
Filed:
Oct. 30, 2002
Method and apparatus for lowering bus clock frequency in a complex integrated data processing system
Richard T. Witek, Austin, TX (US);
Suzanne Plummer, Austin, TX (US);
James Joseph Montanaro, Austin, TX (US);
Stephen Charles Kromer, Austin, TX (US);
Kathryn Jean Hoover, Austin, TX (US);
Richard T. Witek, Austin, TX (US);
Suzanne Plummer, Austin, TX (US);
James Joseph Montanaro, Austin, TX (US);
Stephen Charles Kromer, Austin, TX (US);
Kathryn Jean Hoover, Austin, TX (US);
Advanced Micro Devices, Inc., Sunnyvale, CA (US);
Abstract
A data processing system () comprises a system bus (), a plurality of devices () coupled to the system bus (), a bus monitor circuit (), and a clock generator (). The plurality of devices () includes at least one bus master () which is capable of performing accesses on the system bus (). The bus monitor circuit () is coupled to the at least one bus master (), and has an output for providing a bus idle signal to indicate that no bus master is attempting to perform an access on the system bus (). The clock generator () has an output coupled to at least one of the plurality of devices () and provides a bus clock signal having a first frequency when the bus idle signal is inactive and having a second frequency lower than the first frequency when the bus idle signal is active.