Dram architecture enabling refresh and access operations in the same bank

Abstract

To provide a DRAM that reduces access latency during refresh and performs refresh for any non-accessed bank in parallel with normal memory accesses. Furthermore, the DRAM allows access to a bank that is undergoing refresh. The DRAM includes a circuit for directing refresh execution by comparing bank address of both access and refresh operations, a circuit for specifying a bank address of the memory cells to be refreshed, a circuit for addressing a row address of the memory cells to be refreshed in the specified bank, a means for refreshing the memory cells, and a means for accessing the memory cells directly after refresh without denying the access request.