The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2006

Filed:

Sep. 10, 2002
Applicants:

Richard P. Burnley, Mountain View, CA (US);

Shizuka Oda, San Leandro, CA (US);

Andy H. Gan, San Jose, CA (US);

Inventors:

Richard P. Burnley, Mountain View, CA (US);

Shizuka Oda, San Leandro, CA (US);

Andy H. Gan, San Jose, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); G06F 9/45 (2006.01);
U.S. Cl.
CPC ...
Abstract

Method and apparatus for timing modeling is described. More particularly, sub-processes for obtaining timing information are described. Each of these sub-process is limited to a portion of a gasket module for coupling an embedded device to a host device, and each of these sub-process may be limited to a lithographic process dimension or adjusted accordingly. By dividing timing information gathering into sub-process, output from each of the sub-process may be combined with timing information provided with an embedded core to determine path delays.


Find Patent Forward Citations

Burnley, Richard. (2006). Method and apparatus for timing modeling (U.S. Patent No. 7092865). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7092865

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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