The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2006
Filed:
Jun. 04, 2004
Prasanna Venkat Srinivas, Cupertino, CA (US);
Atul Srinivasan, Santa Clara, CA (US);
Shankar Krishnamoorthy, Saratoga, CA (US);
Prasanna Venkat Srinivas, Cupertino, CA (US);
Atul Srinivasan, Santa Clara, CA (US);
Shankar Krishnamoorthy, Saratoga, CA (US);
Sierra Design Automation, Inc., Santa Clara, CA (US);
Abstract
A method and apparatus are presented that can analyze the performance of an integrated circuit design at multiple corners, under multiple modes, and for multiple objectives efficiently and simultaneously. The extraction, timing analysis, and optimization functions are integrated into a mechanism that provides a novel problem formulation. A plurality of virtual timing graphs are maintained and updated simultaneously by providing a data structure that can efficiently store operating data for an arbitrary number of conditions at each node. This data structure is populated according to the design, and as optimizations are made, the operating data for all design conditions is updated simultaneously. Timing violations can be reported across all corners and modes. By integrating this multi-corner multi-mode analysis with circuit optimization, a convergent mechanism is provided. In this way, design constraints are evaluated simultaneously for an arbitrary number of design conditions.