The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 15, 2006

Filed:

May. 13, 2002
Applicants:

Sakyun Hwang, Fullerton, CA (US);

Seong-ho Lee, Fullerton, CA (US);

Christopher R. Pasqualino, Glendora, CA (US);

Stephen G. Petilli, Pasadena, CA (US);

Hao O. Phung, Alhambra, CA (US);

Inventors:

Sakyun Hwang, Fullerton, CA (US);

Seong-Ho Lee, Fullerton, CA (US);

Christopher R. Pasqualino, Glendora, CA (US);

Stephen G. Petilli, Pasadena, CA (US);

Hao O. Phung, Alhambra, CA (US);

Assignee:

Broadcom Corporation, Irvine, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 7/00 (2006.01); H04L 25/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A deserializer that deserializes a high data rate bit stream to extract a set of bits contained therein includes a data sampler, a serial-to-parallel converter, a windowing block, and a phase error detection block. The data sampler over samples the high data rate bit stream to produce a serial group of samples corresponding to the set of bits of the high data rate bit stream. The serial-to-parallel converter couples to the data sampler and converts the serial group of samples into a parallel group of samples. The windowing block receives the parallel group of samples and produces output bits corresponding to the set of bits. The phase error detection block couples to the windowing block, detects errors in the alignment of the overlapping sampling windows of the windowing block, and directs the windowing block to adjust the operation. The phase error detection block and the windowing block compensate for bit stream jitter and intersymbol interference.


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