The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2006
Filed:
Sep. 29, 2004
Douglas P. Sheppard, Southlake, TX (US);
Douglas P. Sheppard, Southlake, TX (US);
Other;
Abstract
A memory array employing shared bit-lines. A memory is formed from an array of plural bit-cells organized as plural columns and plural rows. Plural word-lines are aligned with each for the rows, and each is electrically coupled to a discrete fraction of the bit-cells its corresponding row. The memory also includes plural bit-lines that are aligned with the plural columns. Every bit-line is electrically coupled to all of the bit-cells that lie along at least one column. In addition, at least a first one of the bit-lines is further electrically coupled to all of the bit-cells in an additional column. That bit-line is coupled such that every one of the plural bit-cells, that lie along any given row that are coupled to it, is coupled to a unique word-line from the other bit-cells coupled thereto. The shared bit-line invention is applicable to single and multiple port memory arrays. It is applicable to all memory array technologies including, but not limited to, SRAMs and DRAMs.