On-chip differential multi-layer inductor

Abstract

An on-chip differential multi-layer inductor includes a 1partial winding on a 1layer, a 2partial winding on the 1layer, a 3partial winding on a 2layer, a 4partial winding on the 2layer, and an interconnecting structure. The 1and 2partial windings on the 1layer are operably coupled to receive a differential input signal. The 3and 4partial windings on the 2layer are each operably coupled to a center tap. The interconnecting structure couples the 1, 2, 3and 4partial windings such that the 1and 3partial windings form a winding that is symmetrical about the center tap with a winding formed by the 2and 4partial windings. By designing the on-chip differential multi-layer inductor to have a desired inductance value, a desired Q factor, and a desired operating rate, a desired resonant frequency and corresponding desired capacitance value can be determined. Having determined the electrical parameters of the multi layer established, the geometric shapes of the windings, number of windings, number of layers to support the inductor, and the interconnecting structure may be determined.