The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 15, 2006
Filed:
Jul. 03, 2003
Uming Ko, Plano, TX (US);
David B. Scott, Plano, TX (US);
Sumanth Gururajarao, Dallas, TX (US);
Hugh Mair, Fairview, TX (US);
Uming Ko, Plano, TX (US);
David B. Scott, Plano, TX (US);
Sumanth Gururajarao, Dallas, TX (US);
Hugh Mair, Fairview, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
State retention registers for use in low-power standby modes of digital IC operation are provided, wherein: a differential circuit (M−M; M−M) is used to load the shadow latch from the normal functional latch; the signal (REST, RESTZ) used to restore data from the shadow latch to the normal functional latch is a 'don't care' signal while the shadow latch is retaining the data during low-power standby mode; retained data from the shadow latch is restored to the normal functional latch via a transistor gate connected to a node (N) of the shadow latch where the retained data is provided; a power supply (VDD) other than the shadow latch's power supply (VRETAIN) powers the data restore operation; and the normal functional latch is operable independently of the operational states of the high Vtransistors (M, M, Mand M; M, M, Mand M) used to implement the state retention functionality. In addition, an isolation apparatus is provided to retain an output of a logic module while the logic module is powered-down.