The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2006
Filed:
Nov. 24, 2003
Anthony Correale, Jr., Raleigh, NC (US);
David S. Kung, Chappaqua, NY (US);
Douglass T. Lamb, Cary, NC (US);
Zhigang Pan, Austin, TX (US);
Ruchir Puri, Peekskill, NY (US);
Anthony Correale, Jr., Raleigh, NC (US);
David S. Kung, Chappaqua, NY (US);
Douglass T. Lamb, Cary, NC (US);
Zhigang Pan, Austin, TX (US);
Ruchir Puri, Peekskill, NY (US);
International Business Machines Corp., Armonk, NY (US);
Abstract
A method and program product for optimizing level converter placement in a multi supply integrated circuit. Each level converter is placed at a minimum power point to minimize net power and transitional delay from a first (low) voltage net source through the level converter and to a second (higher) voltage net sink. Then, inefficient level converters are eliminated. Level converters with fanin cones below a selected minimum cone size are deleted and low voltage sources to the deleted level converter reverted. Higher voltage level circuit elements receiving inputs from multiple level converters are replaced with equivalent low voltage circuit elements. Low voltage buffer driving level converters are both replaced by a single said level converter.