Architecture and method for output clock generation on a high speed memory device

Abstract

An output clock for a memory device having a read latency more than one clock cycle includes a clock generator at a central location on the device. A clock channel couples the clock generator to output structures. A timing path emulates the address/data paths in the memory, and is responsive to an address emulation signal produced by the clock generator to provide dummy data near the output structures. An output clock signal with an adjustable phase and a dummy data reference clock signal on the input of the clock channel are generated. A phase detector near the output structures, determines whether the output clock is early, late or on time with respect to the dummy data. Logic signals are produced at the phase detector, and returned to the clock generator for adjusting the relative phase of the output clock signal.