The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2006

Filed:

Feb. 24, 2005
Applicants:

Takahiro Matsuzawa, Ibaraki, JP;

Yoritaka Saitoh, Ibaraki, JP;

Masayuki Hira, Ibaraki, JP;

Inventors:

Takahiro Matsuzawa, Ibaraki, JP;

Yoritaka Saitoh, Ibaraki, JP;

Masayuki Hira, Ibaraki, JP;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The objective of this invention is to provide a static memory cell and an SRAM device that can improve the write margin while preventing degradation of the static noise margin. By turning on/off transistor Qpit is possible to control the drop in voltage due to the threshold voltage of transistor QnFor example, in read mode, when it is necessary to hold the stored data while setting word line WL to the high level, transistor Qpis turned off; the drivability of transistor pair QnQnis decreased, thereby increasing the static margin. In the case of rewriting the stored data, transistor Qpis turned on; the drivability of transistor pair Qn, Qnis increased, thereby increasing the write margin. As a result, it is possible to improve the performance of both the static noise margin and the write margin.


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