The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2006

Filed:

Mar. 28, 2003
Applicants:

Masuyuki Ohta, Mobara, JP;

Kazuhiko Yanagawa, Mobara, JP;

Kazuhiro Ogawa, Mobara, JP;

Keiichiro Ashizawa, Mobara, JP;

Masahiro Yanai, Mobara, JP;

Nobutake Konishi, Mobara, JP;

Katsumi Kondo, Hitachinaka, JP;

Masahito Ohe, Mobara, JP;

Sukekazu Aratani, Hitachi, JP;

Hagen Klausmann, Hitachi, JP;

Inventors:

Masuyuki Ohta, Mobara, JP;

Kazuhiko Yanagawa, Mobara, JP;

Kazuhiro Ogawa, Mobara, JP;

Keiichiro Ashizawa, Mobara, JP;

Masahiro Yanai, Mobara, JP;

Nobutake Konishi, Mobara, JP;

Katsumi Kondo, Hitachinaka, JP;

Masahito Ohe, Mobara, JP;

Sukekazu Aratani, Hitachi, JP;

Hagen Klausmann, Hitachi, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02F 1/1343 (2006.01); G02F 1/1337 (2006.01);
U.S. Cl.
CPC ...
Abstract

A liquid crystal display device includes a pair of substrates sandwiching of a liquid crystal layer, plural scanning signal lines and plural video signal lines formed on one of the pair of substrates, and plural pixel regions formed as an area surrounded by an adjacent two of the plural scanning signal lines and an adjacent two of the plural video signal lines. At least a pixel electrode is formed on the one of the pair of substrates in each of the pixel regions, a plurality of counter electrodes is formed on one of the pair of substrates in each of the pixel regions, and at least a counter voltage signal line connects the counter electrodes formed on one of the pair of substrates. The counter voltage signal line is arranged in an overlapping relation with at least one of the scanning signal lines in plan view.


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