The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2006

Filed:

Apr. 16, 2003
Applicants:

Ammisetti V. Prasad, Austin, TX (US);

Karl Thompson, Converse, TX (US);

John Laurence Melanson, Austin, TX (US);

Shyam Somayajula, Austin, TX (US);

Inventors:

Ammisetti V. Prasad, Austin, TX (US);

Karl Thompson, Converse, TX (US);

John Laurence Melanson, Austin, TX (US);

Shyam Somayajula, Austin, TX (US);

Assignee:

Cirrus Logic, Inc., Austin, TX (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 27/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A sample and hold circuit including a sampling capacitor for storing a sample of an input signal, an output stage for outputting the sample stored on the sampling capacitor; and input circuitry for sampling the input signal and storing the sample on the sampling capacitor. The input circuitry includes an autozeroing input buffer which selectively samples the input signal during a first operating phase and holds a sample of the input signal during a second operating phase. The autozeroing input buffer cancels any offset error. The input circuitry also includes switching circuitry for selectively coupling the sampling capacitor with an input of the sample and hold circuitry during the second operating phase and to an output of the autozeroing input buffer during the first operating phase.


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