The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2006

Filed:

Mar. 26, 2004
Applicant:

Tomohiko Koto, Kasugai, JP;

Inventor:

Tomohiko Koto, Kasugai, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/0175 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor integrated circuit for decreasing level fluctuation in an output signal of a level conversion circuit. The level conversion circuit has a pair of series-connected transistors including a first MOS transistor and a second MOS transistor and a further pair of series-connected transistors including a third MOS transistor and a fourth MOS transistor. The level conversion circuit generates a first output signal from a node connecting the first and second MOS transistors and a second output signal from a node connecting the third and fourth transistors. A differential amplification circuit functions in accordance with the first and second output signals. The first and fourth MOS transistors each have a gate for receiving a first input signal. The second and third MOS transistors each have a gate for receiving a second input signal having a phase inverted from the phase of the first input signal.


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