The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2006
Filed:
Nov. 17, 2003
Narain D. Arora, San Jose, CA (US);
Rimma A. Pirogova, San Jose, CA (US);
Narain D. Arora, San Jose, CA (US);
Rimma A. Pirogova, San Jose, CA (US);
Siprosys, Inc., San Jose, CA (US);
Abstract
A system that facilitates non-invasive in-line characterization of parameters of VLSI circuit interconnects is provided. A plurality of micro-electro-mechanical system (MEMS) cantilevers apply voltage(s) to VLSI circuit interconnect(s) without physical contact thereto. A measuring component measures deflection characteristics of the cantilevers, the deflection(s) correspond to electrical forces generated from the applied voltage(s) as passed through VLSI circuit interconnect(s). A component computes characteristics of the VLSI interconnect based at least in part upon the measured deflection characteristics.