The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7087487 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 08, 2006

Filed:

Mar. 03, 2003
Applicant:

Katsumi Mori, Sakata, JP;

Inventor:

Katsumi Mori, Sakata, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method, for fabricating a semiconductor device including a memory region and a logic circuit region including a periphery circuit, includes: forming sidewall-like control gates on both side surfaces of a first conductive layer at least in a memory region with an ONO film interposed therebetween, respectively; patterning a first conductive layer in a logic circuit region and thereby forming a gate electrode of a MOS transistor; forming a second insulating layer above the control gates; applying anisotropic etching to the second insulating layer, and thereby at least partially exposing the control gates; and on the exposed surfaces of the control gates, forming a silicide layer.


Find Patent Forward Citations

Mori, Katsumi. (2006). Method for fabricating nonvolatile memory device and method for fabricating semiconductor device (U.S. Patent No. 7087487). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7087487

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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