The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 08, 2006

Filed:

Jul. 18, 2003
Applicant:

Peyman Hadizad, Scottsdale, AZ (US);

Inventor:

Peyman Hadizad, Scottsdale, AZ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/337 (2006.01);
U.S. Cl.
CPC ...
Abstract

In one embodiment, a method for fabricating a compound semiconductor vertical FET device includes forming a first trench in a body of semiconductor material, and forming a self-aligned second trench within the first trench to define a channel region. A doped gate region is then formed on the sidewalls and the bottom surface of the second trench. Source regions are formed on opposite sides of the trench structure. Localized gate contact regions couple individual doped gate regions together. Contacts are then formed to the localized gate contact regions, the source regions, and an opposing surface of the body of semiconductor material. The method provides a compound semiconductor vertical FET structure having enhanced blocking capability.


Find Patent Forward Citations

Hadizad, Peyman. (2006). Method of making a vertical compound semiconductor field effect transistor device (U.S. Patent No. 7087472). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7087472

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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