The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 08, 2006
Filed:
Sep. 03, 2004
Chih-yu Peng, Hsinchu, TW;
Wei-chuan Lin, Taipei, TW;
Chian-chih Hsiao, Taipei Hsien, TW;
Ta-ko Chuang, Taichung, TW;
Chun-hung Chu, Feng Yuan, TW;
Chih-lung Lin, Taichung, TW;
Chin-mao Lin, Chiayi, TW;
Chih-Yu Peng, Hsinchu, TW;
Wei-Chuan Lin, Taipei, TW;
Chian-Chih Hsiao, Taipei Hsien, TW;
Ta-Ko Chuang, Taichung, TW;
Chun-Hung Chu, Feng Yuan, TW;
Chih-Lung Lin, Taichung, TW;
Chin-Mao Lin, Chiayi, TW;
Hannstar Display Corp., , TW;
Abstract
A method of controlling the capacitance of a thin film transistor liquid crystal display (TFT-LCD) storage capacitor is disclosed. In certain embodiments, the method includes i) forming a silicon island and a bottom electrode on the transparent substrate, the silicon island having an undoped region located on the central portion, and two doped regions respectively located on both sides, ii) forming a first silicon nitride layer on the transparent substrate, and iii) forming a stacked layer comprising a second silicon nitride layer and a conductive layer on the undoped region of the silicon island, and the first conductive layer of the stacked layer serving as a gate of a thin film transistor, wherein an etching selectivity ratio of the conductive layer over the dielectric layer is not less than about 5.0.