The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2006
Filed:
Jul. 03, 2000
Venkata K. R. Chiluvuri, Austin, TX (US);
Alexander Mikhailovich Marchenko, Moscow, RU;
Mikhail Anatolievich Sotnikov, Moscow, RU;
Venkata K. R. Chiluvuri, Austin, TX (US);
Alexander Mikhailovich Marchenko, Moscow, RU;
Mikhail Anatolievich Sotnikov, Moscow, RU;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A method of compacting a circuit layout includes determining a critical path of the circuit layout, the critical path having a length not less than a length of each other path of the circuit layout. The method further includes representing the critical path to include a plurality of vertices and a plurality of edges, each one of the vertices being coupled to another of the vertices by an edge, the plurality of vertices including a flexible vertex corresponding to a flexible element of the circuit layout, the plurality of edges including a first shear edge. The method further includes representing the flexible vertex to include a first jogging edge. The method further includes determining an optimal cutest of the graph of the critical path, the cutest including at least one of the group consisting of the first jogging edge and the first shear edge.