The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2006
Filed:
Feb. 18, 2003
Applicants:
Nabeel Shirazi, San Jose, CA (US);
Singh Vinay Jitendra, Fremont, CA (US);
Inventors:
Nabeel Shirazi, San Jose, CA (US);
Singh Vinay Jitendra, Fremont, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01);
U.S. Cl.
CPC ...
Abstract
Method and apparatus for hardware co-simulation clocking is described. More particularly, single-step clocking is used to load one or more test vectors and to output test results from such test vectors after processing. The test vectors are processed with the hardware using a free-running clock, for example to speed up test time and to generate information related to operational speed. A simulation of the hardware is used, where single-step clocking out the test results facilitates verification of the hardware test results with simulation test results.