The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7085964 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 01, 2006

Filed:

Feb. 20, 2001
Applicants:

Laurent Fournier, Givat Elah, IL;

Shai Rubin, Haifa, IL;

Inventors:

Laurent Fournier, Givat Elah, IL;

Shai Rubin, Haifa, IL;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for functional verification of a design for a parallel processing device includes receiving a sequence of single instructions from a dynamic test program generator, and assembling a plurality of the instructions from the sequence into an instruction word, in accordance with predetermined rules applicable to the parallel processing device. The instruction word is input to a simulator of the parallel processing device so as to determine a response of the device to the instruction word.


Find Patent Forward Citations

Fournier, Laurent. (2006). Dynamic test program generator for vliw simulation (U.S. Patent No. 7085964). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7085964

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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