The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7085949 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 01, 2006

Filed:

Sep. 14, 2003
Applicants:

William Mar, Taipei Hsien, TW;

Luke Wen, Taipei Hsien, TW;

Inventors:

William Mar, Taipei Hsien, TW;

Luke Wen, Taipei Hsien, TW;

Assignee:

VIA Technologies Inc., Taipei Hsien, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/12 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and related apparatus for providing a clock synchronized with an input signal. The method includes generating an estimated rate according to transitions in the input signal, processing a dithering step for updating the estimated rate by multiplying it with a predetermined ratio, and adjusting the frequency of the clock according to the updated estimated rate. The predetermined ratios used in repeated dithering steps are modified according to a predetermined rule such that the predetermined ratio is different when the dithering steps are repeated.


Find Patent Forward Citations

Mar, William. (2006). Method and related apparatus for locking phase with estimated rate modified by rate dithering (U.S. Patent No. 7085949). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7085949

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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