Programmable prefetching of instructions for a processor executing a non-procedural program

Abstract

A programmable prefetch mechanism is presented for prefetching instructions for a processor executing a program, and in particular a non-procedural program such as object-oriented code. The prefetch mechanism includes prefetching instructions from memory which are sequential instructions from where the processor is currently executing in a sequence of instructions of the program, and when the prefetching encounters a new update prefetch stream (UPS) instruction, the prefetching includes executing the UPS instruction and subsequent thereto, branching to a new memory address for prefetching of at least one non-sequential instruction from memory for execution by the processor. The UPS instruction can be inserted into the program at compile time and when executed causes the loading of a prefetch buffer in the prefetch mechanism which in one embodiment includes a set associative array of x,y address pairs. When an incremented prefetch address is matched to an x address of the array, the prefetching branches to the new memory address y paired with the matching x address in the prefetch buffer. In this manner, cache misses associated with unconditional branches to non-sequential instructions are avoided.