The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2006
Filed:
Dec. 23, 2003
Manjula N. Variyam, Plano, TX (US);
Manjula N. Variyam, Plano, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
Embodiments of the present invention may provide ways and uses for correlating actual wire bonding machine adjustment parameters to inputs needed for FEA simulations in modeling actual wire bonding operations of a specified capillary design and wire bonding machine. Simulations of wire bonding operations using the specified capillary design are performed with a range of inputs (e.g., capillary displacement, wire yield strength) to develop empirical equations relating to the simulations. Actual wire bonding operations are performed using the specified capillary design with ranges of the actual wire bonding machine adjustment parameters, and the results provide empirical equations relating to the actual wire bonding machine adjustment parameters. The empirical equations are combined to provide empirical equations for the simulation inputs as functions of the actual wire bonding machine adjustment parameters. Such equations may aid in performing chip failure analysis and/or may be incorporated into design rules.