The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2006

Filed:

May. 23, 2005
Applicants:

Warren D. Dyckman, Peekskill, NY (US);

Edward R. Pillai, Wappingers Falls, NY (US);

Daniel P. O'connor, Poughkeepsie, NY (US);

Inventors:

Warren D. Dyckman, Peekskill, NY (US);

Edward R. Pillai, Wappingers Falls, NY (US);

Daniel P. O'Connor, Poughkeepsie, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H05K 7/02 (2006.01); H01L 29/00 (2006.01); H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is a method and structure for locally powering a semiconductor chip within a package. The structure and method incorporate a local voltage regulator mounted adjacent a semiconductor chip on a top surface of a carrier. The voltage regulator is electrically connected to a power plane disposed within the carrier. The voltage regulator continuously senses the reflected voltage of the power plane at a regulated output port and actively cancels time domain noise within its operational bandwidth. Mounting the voltage regulator on top of the carrier adjacent to the chip minimizes loop inductance between the regulator and power plane and also minimizes delay caused by impedance of the power plane on the current flowing to the chip.


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