The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2006

Filed:

Oct. 23, 2003
Applicants:

Joerg Kirchner, Mauern, DE;

Thomas Keller, Freising, DE;

Christian Schimpfle, Wartenberg, DE;

Inventors:

Joerg Kirchner, Mauern, DE;

Thomas Keller, Freising, DE;

Christian Schimpfle, Wartenberg, DE;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G05F 1/613 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention relates to a DC/DC converter including an input to which an input voltage Vin is applied, a inductance L whose one terminal is connected to the input, a first controllable switch Nvia which the other terminal of the inductance is connectable to a reference potential Vss, a second controllable switch Pvia which the other terminal of the inductance is connectable to the output of the converter, and a regulator circuitconfigured so that it is able to control the two switches in regulating the output voltage of the DC/DC converter to a predetermined wanted value. The second controllable switch is a PMOS-FET. The regulator circuit is configured so that when the input voltage is higher than the desired value of the output voltage, the gate of the PMOS-FET is permanently connected to a voltage which is larger than the difference between the input voltage and the threshold voltage of the PMOS-FET, it connecting the back gate of the PMOS-FET permanently to a voltage which is larger than the expression input voltage plus threshold voltage of the PMOS-FET minus the diode voltage of a pn junction of the PMOS-FET and timing the first controllable switch with a specific duty cycle so that the output voltage attains the wanted value. The converter in accordance with the invention now permits achieving both an increase and decrease in the input voltage. It can be put to use preferably in conjunction with battery-powered devices for which a wanted voltage is specified.


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