The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 01, 2006
Filed:
Jun. 23, 2004
Cheol Hwan Park, Seoul, KR;
Sang Ho Woo, Kyoungki-do, KR;
Chang Rock Song, Kyoungki-do, KR;
Dong Su Park, Kyoungki-do, KR;
Tae Hyeok Lee, Kyoungki-do, KR;
Cheol Hwan Park, Seoul, KR;
Sang Ho Woo, Kyoungki-do, KR;
Chang Rock Song, Kyoungki-do, KR;
Dong Su Park, Kyoungki-do, KR;
Tae Hyeok Lee, Kyoungki-do, KR;
Hynix Semiconductor Inc., Kyoungki-do, KR;
Abstract
Disclosed is a method of manufacturing a semiconductor device. The method includes the steps of forming a gate in a cell region and a peripheral region of a substrate, depositing a buffer oxide layer on the gate and the substrate, annealing a resultant structure of the substrate, depositing a nitride spacer layer on the buffer oxide layer, depositing an oxide spacer layer on the nitride spacer layer, forming an oxide spacer at the peripheral region of the substrate, and removing the oxide spacer layer remaining in the cell region. The annealing step is additionally carried out after depositing the buffer oxide layer so as to improve the interfacial surface characteristic and film quality, so that oxide etchant is prevented from penetrating into the silicon substrate during the wet dip process. Unnecessary voids are prevented from being created in the silicon substrate.