The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 01, 2006

Filed:

Feb. 24, 2005
Applicant:

Justin F. Gaynor, San Jose, CA (US);

Inventor:

Justin F. Gaynor, San Jose, CA (US);

Assignee:

Novellus Systems, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Method and apparatus for using a silylating agent after exposure to an oxidizing environment for repairing damage to low-k dielectric films are described. Plasma photoresist removal, or ashing, may damage bonds in the low-k materials, which may lead to a significant increase in the dielectric constant of the materials. The silylating agent may be used to repair damage to the low-k films after the ashing process. Additionally, a curing process using an oxidizing environment may damage bonds in low-k materials, which may subsequently be repaired by a silylating process. The described method and apparatus may be used with low-k dielectric films including hydrophobic porous oxide films. A chamber for processing a wafer in an oxidizing environment and subsequently performing a silylation process includes an oxidizing agent inlet and a silylating agent inlet. Additionally, a chamber for performing an etch process, processing a wafer in an oxidizing environment, and subsequently performing a silylation process includes an oxidizing agent inlet, a silylating agent inlet, and an etch gas inlet. A cluster tool can include a chamber for processing a wafer in an oxidizing environment and subsequently performing a silylation process, a wafer in/out module, and may include additional processing modules such as etch modules, deposition modules for depositing low-k layers, and deposition modules for depositing cap layers.


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