The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 25, 2006
Filed:
Nov. 10, 2003
Michael J. Saunders, Ft. Collins, CO (US);
Norman E. Mause, Ft. Collins, CO (US);
C. Chip Brewster, Ft. Collins, CO (US);
Michael J. Saunders, Ft. Collins, CO (US);
Norman E. Mause, Ft. Collins, CO (US);
C. Chip Brewster, Ft. Collins, CO (US);
LSI Logic Corporation, Milpitas, CA (US);
Abstract
A method of generating a schematic driven layout for an integrated circuit design includes steps of: (a) receiving as input a representation of a integrated circuit design comprising a hierarchy of blocks; (b) selecting a block in the hierarchy of blocks that requires a physical design and that contains no missing components; (c) generating a physical design for the selected block so that the selected block is no longer a missing component of any other block; and (d) repeating steps (b) and (c) until a physical design has been generated for each block in the hierarchy of blocks.