The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 25, 2006

Filed:

Oct. 16, 2001
Applicants:

Jeroen Anton Johan Leijten, Eindhoven, NL;

Marco Jan Gerrit Bekooij, Eindhoven, NL;

Adrianus Josephus Bink, Eindhoven, NL;

Johan Sebastiaan Henri Van Gageldonk, Eindhoven, NL;

Jan Hoogerbrugge, Eindhoven, NL;

Bart Mesman, Eindhoven, NL;

Inventors:

Jeroen Anton Johan Leijten, Eindhoven, NL;

Marco Jan Gerrit Bekooij, Eindhoven, NL;

Adrianus Josephus Bink, Eindhoven, NL;

Johan Sebastiaan Henri Van Gageldonk, Eindhoven, NL;

Jan Hoogerbrugge, Eindhoven, NL;

Bart Mesman, Eindhoven, NL;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 15/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates to a digital signal processing apparatus comprising a plurality of available hardware resource means and a first instruction set means having access to said available hardware resource means, so that at least a part of said hardware resource means execute operations under control of said first instruction set means, and further comprising a second instruction set means having access to only a predetermined limited subset of said plurality of available hardware resource means, so that at least a part of said predetermined limited subset of said hardware resource means execute operations under control of said second instruction set means. Further, the present invention relates to a method for processing digital signals in a digital signal processing apparatus comprising a plurality of available hardware resource means, wherein at least a part of said hardware resource means execute operations under control of a first instruction set, and wherein at least a part of a predetermined limited subset of said plurality of available hardware resource means execute operations under control of a second instruction set having access to only said predetermined limited subset of said hardware resource means.


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