Decoder for decoding symmetric/asymmetric delay modulation signal and the method thereof

Abstract

The invention relates to a decoder for decoding a received signal to obtain a corresponding decoded bit series. The signal comprises a plurality of pulses. The decoder comprises a memory, a counting module, a transform module, and a logic module. The memory is for storing a predetermined look-up table; the look-up table comprises plural kinds of edge time duties and the corresponding decoded bit combinations thereof. The counting module is for measuring the edge time duty between high edges and low edges of adjacent pulses of the signal, so as to obtain a first and a second time series. The transform module, according to the look-up table, is for translating the first time series to a first decoded series, and the second time series to a second decoded series. The logic module is for performing a corresponding logic operation on the first and the second decoded series, so as to obtain the decoded bit series.