The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 18, 2006
Filed:
May. 15, 2003
Yoanna Baumgartner, Austin, TX (US);
Sundeep Chadha, Austin, TX (US);
Richard Nicholas Iachetta, Jr., Pflugerville, TX (US);
Hien Minh Le, Cedar Park, TX (US);
Kirk Edward Morrow, Austin, TX (US);
Yoanna Baumgartner, Austin, TX (US);
Sundeep Chadha, Austin, TX (US);
Richard Nicholas Iachetta, Jr., Pflugerville, TX (US);
Hien Minh Le, Cedar Park, TX (US);
Kirk Edward Morrow, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system and a method are provided for implementing a power-saving sleep mode in a synchronous circuit core having multiple clock domains including primary and secondary clock domains. The primary clock domain has states of awake, asleep, doze, and waking. The doze and waking states are transient states between the awake and asleep states. One or more secondary clock domains each have states of secondary awake and secondary asleep. The doze and waking states are used to eliminate race conditions between the primary and secondary clock domains. If the core has two or more secondary clock domains, the secondary clock domains each have an additional state of sleep-pending. The sleep-pending state is a transient state between the secondary awake and secondary asleep states. One or more synchronization logics are coupled between the primary and secondary clock domains.