The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2006

Filed:

May. 24, 2002
Applicants:

Chandra M. R. Thimmannagari, Fremont, CA (US);

Sorin Iacobovici, San Jose, CA (US);

Rabin A. Sugumar, Sunnyvale, CA (US);

Robert Nuckolls, Santa Clara, CA (US);

Inventors:

Chandra M. R. Thimmannagari, Fremont, CA (US);

Sorin Iacobovici, San Jose, CA (US);

Rabin A. Sugumar, Sunnyvale, CA (US);

Robert Nuckolls, Santa Clara, CA (US);

Assignee:

Sun Microsystems, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

A technique for flattening architectural register windows into flattened space depending on a current window pointer to a register window is provided. The technique involves converting an n-bit value of a particular register in a register window to an x-bit value dependent on the current window pointer, where x is greater than n, and where the x-bit value is used for register dependency checking among a plurality of instructions.


Find Patent Forward Citations

Thimmannagari, Chandra M. R.. (2006). Register window flattening logic for dependency checking among instructions (U.S. Patent No. 7080237). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7080237

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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