The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 18, 2006
Filed:
Mar. 10, 2003
Larry L. Byers, Apple Valley, MN (US);
Paul B. Ricci, Coto Fe Caza, CA (US);
Joseph G. Kriscunas, Dove Canyon, CA (US);
Joseba M. Desubijana, Minneapolis, MN (US);
Gary R. Robeck, Albertville, MN (US);
Michael R. Spaur, Dana Point, CA (US);
David M. Purdham, Brooklyn Park, MN (US);
Larry L. Byers, Apple Valley, MN (US);
Paul B. Ricci, Coto Fe Caza, CA (US);
Joseph G. Kriscunas, Dove Canyon, CA (US);
Joseba M. Desubijana, Minneapolis, MN (US);
Gary R. Robeck, Albertville, MN (US);
Michael R. Spaur, Dana Point, CA (US);
David M. Purdham, Brooklyn Park, MN (US);
Marvell International Ltd., Hamilton, BM;
Abstract
A system for an embedded disk controller is provided. The system includes a first main processor operationally coupled to a high performance bus; a second processor operationally coupled to a peripheral bus; a bridge that interfaces between the high performance and peripheral bus; an external bus controller coupled to the high performance bus and operationally coupled to external devices via an external bus interface; an interrupt controller module that can generate a fast interrupt to the first main processor; a history module coupled to the high performance and peripheral bus for monitoring bus activity; and a servo controller that is coupled to the second processor through a servo controller interface and provides real time servo controller information to the second processor. The second processor may be a digital signal processor that is operationally coupled to the first main processor through an interface.