The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2006

Filed:

May. 11, 1999
Applicants:

Magnus Johansson, Luleå, SE;

Lennart Olsson, Luleå, SE;

Gunnar Bahlenberg, Luleå, SE;

Daniel Bengtsson, Luleå, SE;

Mikael Isaksson, Luleå, SE;

Sven-rune Olofsson, Luleå, SE;

Sven-göran Ökvist, Luleå, SE;

Inventors:

Magnus Johansson, Luleå, SE;

Lennart Olsson, Luleå, SE;

Gunnar Bahlenberg, Luleå, SE;

Daniel Bengtsson, Luleå, SE;

Mikael Isaksson, Luleå, SE;

Sven-Rune Olofsson, Luleå, SE;

Sven-Göran Ökvist, Luleå, SE;

Assignee:

STMicroelectronics NV, Amsterdam, NL;

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B 1/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a multi-carrier system employing OFDM, for example DMT, an adaptive channel equalizer is normally used, operating in the frequency domain. The sampling clock is controlled so that the time delay between the transmitter and the receiver is effectively eliminated. If the information used to control the sampling clock is received from the equalized data stream, it will introduce an ambiguity between the operation of the channel equalizer and the mechanism used to control the sampling clock. Operation of the equalizer can mask an increasing time difference, between transmitter and receiver, which the sample clock controller should be tracking. The present invention eliminates the ambiguities in the operation of the equalizer and sample clock controller by preventing the equalizer from accepting time differences which should be corrected by operation of the sample clock controller.


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