The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 18, 2006

Filed:

Jun. 14, 2002
Applicants:

Cheng-yuan Chang, Taichung, TW;

Jie-hau Huang, Taichung, TW;

Hong-chin Lin, Taipei, TW;

Guu-chang Yang, Taichung, TW;

Yung-hsien Chang, Yunlin, TW;

Hsuan-ching Chao, Keelung, TW;

Inventors:

Cheng-Yuan Chang, Taichung, TW;

Jie-Hau Huang, Taichung, TW;

Hong-Chin Lin, Taipei, TW;

Guu-Chang Yang, Taichung, TW;

Yung-Hsien Chang, Yunlin, TW;

Hsuan-Ching Chao, Keelung, TW;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04L 27/22 (2006.01); H04L 27/06 (2006.01); H04J 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention relates to both of a bi-stage correlation calculation demodulation system, and a fast walsh block demodulation device at a receiver, wherein the bi-stage correlation calculation demodulation system has a characteristic of bi-stage correlation calculation in which the subsequent second-stage correlation calculations are dependent on the first-stage correlation calculation results by utilizing an incomplete orthogonal property within CCK codewords to arrange the CCK codewords operated in the first-stage correlation calculations and second-stage correlation calculations properly and respectively. The fast walsh block demodulation device comprises: a plurality of adders (operators) constructed to be a first-level correlation calculation circuit and a second-level correlation calculation circuit, and a plurality of process modules constructed to be a third-level correlation calculation circuit, the process modules having the functions of picking one maximum value from four values and performing third-level correlation calculation of conventional basic fast walsh block demodulation device.


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